1. Field of Invention
The present invention relates to a self-aligned via structure and the method for manufacturing the structure. More particularly, the present invention relates to a self-aligned via structure and its manufacturing method that can circumvent the restrictions imposed by the extension rules.
2. Description of Related Art
Integrated circuits are now developing towards more precise and complicated functions. As the feature size of a device gets smaller, the design rules for manufacturing such devices become more restrictive. To link up all the devices in the integrated circuit properly, sufficient metallic interconnects must be made on top of the wafer within the limited surface area available. To produce sufficient interconnections, the current trend is to form two or more metallic layers each separated by dielectric layers, then interconnecting different metallic layers through vias.
FIG. 1 is a top view showing a layout of a conventional via structure. In FIG. 1, several vias 11 are distributed on a dielectric layer 10, and the conductive lines 12 (shown by the dash lines) are formed below the dielectric layer 10. The conductive lines 12 are connected electrically to a metallic layer (not shown) on top of the dielectric layer 10 through vias 11. For a conventional via structure 11 design, the extension rules must be referred to. The so-called extension rules are additional dimensions added on to the feature dimensions when the layout of an electric circuit is first planned as to provide enough dimensional tolerance for possible errors arising from various factors in production. For example, it is difficult to make a via align perfectly with the metallic layer below. Therefore, a tolerance within the range of about .+-.0.15 .mu.m must be allowed, for example. Another factor concerns the dimensional bias produced by production equipment. For example, the actual size of the via 11 that comes out from a light exposure may be quite different from the desired via dimensions. Therefore, it is a normal practice to allow a tolerance range, for example, about .+-.0.21 .mu.m, for taking into account the errors produced by the equipment in the production process. As shown in FIG. 1, a tolerance width of d is used around the via 11.
In the conventional production method of vias, whenever some defects are encountered, extension rules are added to the device layout such as a value d in FIG. 1. Such spatial consideration has the impact of severely limiting further miniaturization of the devices. Furthermore, one of the steps in the production of a via is to go through a light exposure step, and light passing through the optical system will undergo diffraction. Therefore, the original shape of the via will be slightly distorted. For example, the corners of the via will be more rounded. The occurrence of such rounding will reduce the actual size of the via, increase etching difficulties and increase the resistance of the via. Alternately, when alignment is carried out, misalignment can occur quite easily, thereby also leading to an increase in the resistance of via and difficulties in etching.
In light of the foregoing, there is a need in the art to provide a better method for forming a via.